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FEATURES 2 s ADC with T/H 4-Channel MUX AD899 Compatible +5 Volt Operation On-Chip Reference 4 s Voltage Output DAC Fast Bus Access Time--75 ns APPLICATIONS Servo Controls Digitally Controlled Calibration Process Control Equipment
A0 A1 VI N A VIN B VI N C VI N D RS INT BUSY ST DGND M U X T/H
8-Bit, 4-Channel Data Acquisition System AD8401
FUNCTIONAL BLOCK DIAGRAM
VDD (+5.0V)
8-BIT ADC 1.25 REF
8-BIT DAC
VOUT
DAC REG CONTROL LOGIC ADC REG
AD8401
RD
CLK
CS
WR
DATA I/O (8 BITS)
AG DAC
AG ADC
GENERAL DESCRIPTION
The AD8401 is a complete data acquisition and control system containing ADC, DAC, 4-channel MUX, and internal voltage reference. Built using CBCMOS, this monolithic circuit offers the user a complete system with very high package density and reliability. The converter is a successive approximation ADC with T/H, and is capable of operating with conversion times as short as 2 s. Analog input bandwidth is 200 kHz, and DAC output voltage settling time is less than 4 s, making the AD8401 capable of controlling servo loops with speed and precision. The 8-bit data interface provides both read and write operation for parallel bus interfaces to microcontrollers and DSP processors. An external 5 MHz clock sets the 2 s conversion rate. Slower clocks reduce the conversion time and the internal power dissipation. The standard control lines: Reset, Busy, Interrupt, Read and Write complete the handshaking signals for microprocessor communication. A start trigger ST input allows precise sampling intervals in synchronous sampling applications.
The input multiplexer addressing is designed for direct interface to the AD899 hard-disk drive, read-channel device with no extra hardware or special software. Analog input range levels are likewise compatible with the AD899. The AD8401 is designed to operate from a single +5 volt supply, which will give an ADC input range of 0 V to 3.0 V, and DAC output range of 0 V to 2.5 V. The AD8401 is offered in the SOIC-28 surface mount package, and is guaranteed to operate over the extended industrial temperature range of -40C to +85C.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD8401-SPECIFICATIONS
ADC ELECTRICAL CHARACTERISTICS unless otherwise noted)
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Offset Error Full-Scale Error Full-Scale/VDD DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Intermodulation Distortion Frequency Response Track/Hold Acquisition Time SNR THD IMD 0 to 200 kHz tAQ 0 -500 10 VIN = 0 V VIN = VDD CS, RD, RS, ST 1.6 40 10 0.4 4.0 10 10 2 Symbol N TUE INL DNL VOSE AE Conditions
(@ VDD = +5.0 V
5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; -40 C TA +85 C,
Min 8 -1 -1 -4 -6 -4 -6
Typ
Max
Units Bits LSB LSB LSB LSB LSB LSB LSB LSB dB dB dB dB ns
3 +1 +1 +4 +6 +4 +6 1 44 48 60 0.1 200 3 +500
TA = +25C TA = Full Temp Range TA = +25C TA = Full Temp Range TA = +25C
ANALOG INPUTS (Applies to Inputs A, B. C, D) Unipolar Input Range VIN Input Current IIN Input Capacitance CIN LOGIC INPUTS Clock Input Current Low Clock Input Current High Input Leakage Current ICKL ICKH IL
V A pF mA A A V V A pF s
LOGIC OUTPUTS (Applies to Outputs DB0-DB7, INT, BUSY) Logic Output Low Voltage VOL IOL = 1.6 mA Logic Output High Voltage VOH IOH = 200 A Output Leakage Current IOZ CS = 1 (Except INT & BUSY) Output Capacitance COZ CS = 1 (Except INT & BUSY) CONVERSION TIME tC External Clock
Specifications subject to change without notice.
Table I. Multiplexer Address Input Decode
A1 0 0 1 1
A0 0 1 0 1
Input Selected VINA VINB VINC VIND
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AD8401 DAC ELECTRICAL CHARACTERISTICS to AG
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Offset Error Full-Scale Error Full-Scale/VDD Load Regulation at Full-Scale DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion ANALOG OUTPUT Output Voltage Range SNR THD OVR 0 Symbol N TUE INL DNL VOSE AE
(@ VDD = +5.0 V 5%, AGDAC = AGADC = 0.0 V; RL = 2 k , CL = 100 pF DAC; -40 C TA +85 C, unless otherwise noted)
Min 8 -1 -1 -2 -2.5 -3 -4 -0.5 -0.2 44 48 +2.5 0.8 2.4 -10 10 10 2 1 2 15 1 60 4 2 4 Typ Max Units Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB dB dB V V V A pF s s s nV s nV s dB mA
Conditions
2 +1 +1 +2 +2.5 +3 +4 +0.5 +0.2
TA = +25C TA = Full Temp Range TA = +25C TA = Full Temp Range TA = +25C
LOGIC INPUTS (Applies to DB0-DB7, CS, WR, RD, RS) Logic Input Low Voltage VIL Logic Input High Voltage VIH Input Leakage Current IL Input Capacitance CIL AC CHARACTERISTICS Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change DAC Glitch Impulse Digital Feedthrough VIN to VOUT Isolation POWER REQUIREMENTS Positive Supply Current
Specifications subject to change without notice.
tS tPOS tNEG
To 1/2 LSB of Final Value 10% to 90% 90% to 10%
f = 50 kHz IDD No Load
13
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AD8401 TIMING ELECTRICAL SPECIFICATIONS unless otherwise noted)
Parameters1, 2, 3 DAC TIMING (See Figure 8 Timing Diagram) WR Pulse Width CS to WR Setup Time CS to WR Hold Time Data Setup Time Data Hold Time ADC TIMING (See Figures 6 and 7 Timing Diagrams) ST Pulse Width ST to BUSY Delay BUSY to INT Delay BUSY to CS Delay CS to RD Setup Time RD Pulse Width4 CS to RD Hold Time Data Access after RD Data Access after RD Bus Relinquish after RD RD to INT Delay RD to BUSY Delay Data Valid after BUSY Data Valid after BUSY Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t13 t14 t15 t16 t17 t17
(@ VDD = +5.0 V
5%, AGDAC = AGADC = 0.0 V; fCLK = 5 MHz; -40 C TA +85 C,
Condition Min 50 0 0 60 0 40 110 30 0 0 75 0 10 10 10 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CL = 20 pF CL = 100 pF
CL = 20 pF CL = 100 pF
75 135 70 85 110 90 135
NOTES 1 All input control signals are specified with t R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V. 3 t14 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2. 4 t15 is determined by t 13. +5V +5V
DBN DBN 3k DGND CL CL DGND
3k DGND 10pF
3k
DBN DBN
3k 10pF DGND
a. High Z to VOH
b. High Z to VOL
a. VOH to High Z
b. VOL to High Z
Figure 1. Load Circuits for Data Access Time Test
ABSOLUTE MAXIMUM RATINGS*
Figure 2. Load Circuits for Bus Relinquish Time Test
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V Input Voltages . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Package Power Dissipation . . . . . . . . . . . . . . (TJ max-TA)/JA Thermal Resistance JA 28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . 53C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Junction Temperature Range (TJ max) . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . +300C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model*
Temperature Range
Package Description 28-Lead SOIC Die
Package Option SOL-28
AD8401AR -40C to +85C AD8401Chips +25C
*The AD8401 contains 1257 transistors.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8401 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD8401
PIN CONFIGURATION
VDD AG DAC VOUT NC A1 RS DB7 DB6 DB5 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 A0 3 VIN A VIN B VIN C VIN D AGADC CLK INT BUSY 6 DB4 10 DB3 11 DB2 12 DGND 13 19 18 17 16 15 ST RD CS WR DB0 7 8 9 10 11 NC = NO CONNECT Die Size 91 X 121 mil = 11,011 sq mil 12 13 14 15 16 17 19 18 20 5 21 22 25 24 23 2
DICE CHARACTERISTICS
1 28 27 26
AD8401AR
Top View (Not to Scale)
22 21 20
DB1 14
PIN DESCRIPTIONS
Pin# 1 2 3 4 5 6 7-12, 14, 15 13 16 17 18 19
Name VDD AGDAC VOUT NC A1 RESET (RS) DB7 to DB0 DGND WR CS RD ST
Description Positive Supply. Nominal value +5 volts. This pad requires 2 bonds for die assembly. The substrate is common with VDD. Analog Ground for the DAC. There is a separate analog ground for the ADC. Voltage Output from the DAC. No Connect. Address Input that controls multiplexer. See Table I for address decode. Active Low Digital Input that clears the DAC register to zero, setting the DAC to minimum scale. It also asynchronously clears the INT line of the ADC. Digital I/O Lines. DB7 (7) is the Most Significant Bit (MSB), for both the ADC and the DAC, and DB0 (15) is the Least Significant Bit (LSB). Digital Ground. Rising Edge Triggered Write Input. Used to load data into the DAC register. Chip Select. Active Low Input Active Low Read Input. When this input is active, ADC data can be read from the part. RD going low starts the ADC conversion. Falling Edge Triggered Start Input. Used for applications requiring precise sample timing. The falling edge of ST starts the conversion and sets the BUSY low. The ST is not gated by CS. ADC Active Low, Status Output. When the ADC is performing a conversion, the BUSY output is low. Active Low Output. The Interrupt output notifies the system that the ADC has completed its conversion. INT goes high on the rising edge of CS or RD. It will also be forced high when RESET is asserted. External Clock Input Pin. Accepts a TTL or 5 V CMOS input logic levels. Analog ADC Ground Four Analog Inputs Address input that controls multiplexer. See Table I for address decode. -5-
20 21
BUSY INT
22 23 27-24 28 REV. 0
CLK AGADC VINA, B, C, D A0
AD8401
OPERATION
The AD8401 is a complete data acquisition and control system. It contains the DAC, a four channel input multiplexer, a track/ hold, an ADC, as well as an internal bandgap reference. It interfaces to the microcontroller via an 8-bit digital I/O port.
D/A CONVERTER SECTION
The DAC is an 8-bit voltage mode DAC with an output that swings from AGDAC to the 1.25 volt bandgap voltage. It uses an R-2R ladder fed by PNP current sources which allow the output to swing to ground so that the DAC operates in a unipolar mode.
AMPLIFIER SECTION
Figure 4 shows the wave forms for a conversion cycle. The track and hold begins holding the input voltage VIN approximately 50 ns after the falling edge of the Start command. The MSB decision is made approximately 50 ns after the second falling edge of the CLK. If tX is greater than 50 ns, then the falling edge of the CLK will be seen as the first falling clock edge. If tX is less than 50 ns, the first MSB conversion will not occur until one clock cycle later. The following bits will each be converted in a similar manner 50 ns after each CLK edge until all eight bits have been converted. After the end of conversion the contents of the ADC SAR register are transferred to the output data latch, the track and hold is returned to the track mode, INT goes low and the SAR is reset.
CS , RD OR ST BUSY 50ns TYP VIN 50ns TYP CLK tx MSB DECISION DB7 LSB DECISION DB0 100ns TYP
The DAC's output is buffered by an internal high speed op amp. The op amps output range is set at 0 V to 2.5 V. The op amp has a 500 ns typical settling time to 0.2% for positive slewing signals. There are differences in settling time for negative slewing signals. Signals going to zero volts will settle slightly slower to ground than is seen in the positive direction.
VDD
20 VOUT 20 n-CH
Figure 4. Operating Waveforms Using the External Clock
ANALOG INPUT
AG DAC
Figure 3. Equivalent Amplifier Output Stage
Current sinking capability is also limited near zero volts in single supply operation. Figure 3 provides an equivalent amplifier output stage schematic.
INTERNAL REFERENCE
The analog inputs of the AD8401 are fed into resistor voltage divider networks with a typical value of 8.5 k. The amplifiers driving these inputs must have an output resistance low enough to drive these nodes without losing accuracy. Taps from the voltage dividers are connected to the track and hold amplifier by the multiplexer switches.
5k VINA 3.57k MUX T/H
An on-chip bandgap is provided as a voltage reference to both the DAC and the ADC. This reference is internal to the AD8401 and is not accessible to the user. It is laser trimmed for both absolute accuracy and temperature coefficients. The reference is internally buffered by a separate control amplifier for both the DAC and ADC to improve isolation between the converters.
DIGITAL I/O
VIND 5k 3.57k AGADC
The 8-bit parallel data I/O port on the AD8401 provides access to both the DAC and the ADC. This port is TTL/CMOS compatible with three-state outputs that are ESD protected. The data format is binary. This data coding applies to both the DAC and the ADC. See the applications information section.
ADC SECTION
Figure 5. Equivalent Analog Input Circuit
TRACK-AND-HOLD AMPLIFIER
A fast successive approximation ADC is used to attain a conversion time of 2 microseconds. Start of conversion is initiated by CS and RD. Following a Start command the BUSY signal will become active and another Start command should not be given until the conversion is complete. The RESET (RS) input does not affect A/D conversion, but the INT (Interrupt or conversion complete) which normally goes active low at the end of a conversion will be forced high by RESET asynchronously.
Following the resistive divider at the input of the AD8401 is a track-and-hold amplifier that captures input signals accurately up to the 200 kHz Nyquist frequency of the ADC. To attain this performance the T/H amplifier must have a much greater bandwidth than the signal of interest. Because of this the user must be careful to band limit the input signal to avoid aliasing high frequency components and noise into the passband. The track-and-hold amplifier is internally controlled by the Start command and is not directly available to the user. After the Start command signal the track-and-hold is placed into the hold mode; it returns to the track mode after the conversion is complete.
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AD8401
CLOCK
t9
CS
The AD8401 uses an external clock that is TTL or 5 V CMOS compatible. The external clock speed is 5 MHz and the duty cycle may vary from 30% to 70%. The external clock can be continuously operated between conversions.
DIGITAL INTERFACE: ADC TIMING AND CONTROL
t10 t 11
RD
t12
t16
BUSY
Two basic ADC operating modes are available with the AD8401. The first mode uses the Start (ST) pin to trigger a synchronized A/D conversion. As soon as the ST pin is asserted, the T/H switches from tracking to the hold mode capturing the present analog input-voltage sample. With the T/H holding the analog sample the successive-approximation analog-to-digital conversion is completed on that sample value. At the end of conversion the T/H returns to the tracking mode. This mode of conversion is ideal for digital signal processing applications where precise interval sampling is necessary to minimize errors due to sampling uncertainty or jitter. A precise clock source can be used to drive the ST input. The second mode of conversion is started by the RD and CS inputs going low, after which the BUSY line puts the microprocessor into a WAIT state until end of conversion. Mode 2 is asserted by connecting the ST pin to logic high. The major advantage of this interface is that a single Read Instruction will start and complete a new analog-to-digital conversion without the need for carefully tailored software delays that often are not portable when software routines are taken to a different processor running at a different clock speed.
t6
ST
t8
INT
t15
t13
DATA HIGH Z OLD DATA
t17
NEW DATA
t14
Figure 7. Mode 2, ADC Interface Timing
Mode 2 Interface
This interface mode can be used with microprocessors that can be put into a WAIT state for at least 2 microseconds. The ST pin must be tied to logic high for proper operation. The microprocessor begins a conversion by executing a READ instruction that asserts the CS and RD pins at the AD8401's decoded address. The AD8401 BUSY output then goes low, forcing the microprocessor's READY (or WAIT) line into a WAIT state. The analog input signal is captured by the T/H on the falling edge of RD. When the conversion is complete (8 clocks later), the BUSY line returns high, and then the P completes its READ of the new data now on the digital output port of the AD8401. Note that while conversion is in progress the ADC places the results from the last conversion (Old Data) on the data bus. The Figure 7 timing diagram details the applicable timing specification requirements.
DIGITAL INTERFACE: DAC TIMING AND CONTROL
t7 tCONVERT
BUSY
t8
INT
t9
CS
t15
t10 t11
RD
t12
Table II shows the truth table for DAC operation. The internal 8-bit DAC register contents are loaded from the data bus when both WR and CS are asserted. The DAC register determines the D/A converter analog-output voltage. The WR input is a positive edge triggered input that loads the bus data into the DAC register subject to the data setup and data hold timing requirements. When CS and WR are low, the DAC register contents will not change with changing data bus values. Figure 8 provides the detail timing diagram for write cycle operation.
Table II. DAC Register Logic
t13
DATA HIGH Z DATA VALID
t14
Figure 6. Mode 1, ADC Interface Timing
Mode 1 Interface
CS H L L X
WR H L L X
RS H H H H L
DAC Function No Effect No Effect DAC Register Updated DAC Register Updated DAC Register Loaded with all Zeros
As shown in Figure 6, the falling edge of the ST pulse initiates a conversion and puts the T/H amplifier into the hold mode. The BUSY signal goes low during the whole A/D conversion time and returns high signaling end of conversion. The INT line can be used to interrupt the microprocessor. When the microprocessor performs a READ to access the AD8401 data, the rising edges of CS or RD will reset the INT output to high after the t15 timing specification. INT can also be used to externally trigger a pulse that activates the CS and RD and places the new data into a buffer or First In First Out FIFO memory. The microprocessor can then load a series of readings from this buffer memory at a convenient time. Care must be taken not to have the ST input high when RD is brought low; otherwise, the AD8401 will not operate properly. Also triggering the ST line a second time before conversion is complete will cause erroneous readings. REV. 0
CS
t2
WR
t1
t3
t4
DATA VALID DATA
t5
Figure 8. Write Cycle Timing
-7-
AD8401
An active low pulse, at any time, on the RESET pin asynchronously forces all DAC register bits to zero. The DAC output voltage becomes zero volts and stays at that value until a new data word is loaded into the DAC register with a new WR command. The equivalent input logic for the DAC register loading is shown in Figure 9.
TO DAC LADDER CS D0 WR RESET INPUT DATA D7
DAC REGISTER
Figure 9. Equivalent DAC Register Control Logic
TYPICAL PERFORMANCE CHARACTERISTICS
1.0 VDD = +5V TA = +25C 120 110 100 90 80 SS = 300 UNITS T A = +25C
LINEARITY ERROR - LSB
0.5
0
UNITS
0 64 128 192 256
70 60 50 40
-0.5
30 20 10
-0.1 DIGITAL INPUT CODE - DECIMAL
0 -4.5
-3.5
-2.5
-1.5 -0.5 0.5 1.5 2.5 FULL SCALE ERROR - LSB
3.5
4.5
Figure 10. ADC Linearity Error vs. Digital Code
1.0 VDD = +5V TA = +25C
Figure 12. ADC Full-Scale Error Histogram
2.5 2.0 V DD = +5V
LINEARITY ERROR - LSB
0.5
ADC FULL-SCALE ERROR - LSB
256
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5
0
-0.5
-0.1 0 64 128 192 DIGITAL INPUT CODE - DECIMAL
-3.0 -50
-25
0
25
50
75
100
TEMPERATURE - C
Figure 11. DAC Linearity Error vs. Digital Code
Figure 13. ADC Full-Scale Error vs. Temperature
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AD8401
240 220 200 180 T A = +25C SS = 300 UNITS
2.5
V DD = +5V T A = +25C R L TO GND
140
UNITS
OUTPUT VOLTAGE - Volts
160
2.0
120 100 80 60 40 20 0 -4 -3 -2 -1 0 1 2 3 4
1.5
1.0 R L TO V DD
0.5
0 10 100 1k LOAD RESISTANCE - 10k 100k
FULL SCALE ERROR - LSB
Figure 14. DAC Full-Scale Error Histogram
3.0 2.5 V DD = +5V
Figure 17. DAC Output Swing vs. Load Resistance
DAC FULL SCALE ERROR - LSB
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -50 x - 3 x x +3
3
5V
2
100
1 0 5V
90
VOUT 5V WR 0
10 0%
0 5V 0
1V 5V 1S
DATA
TIME - 1s/DIV
-25
0
25
50
75
100
TEMPERATURE - C
Figure 18. DAC Output Slew Rate Positive Transition
Figure 15. DAC Full-Scale Error vs. Temperature
4
5V
DAC FULL SCALE OUT CHANGE - LSB
3 2 1 x +3 0 -1 -2 -3 x
V DD = +5V SS = 135 UNITS
3
100
2 1 0 5V
90
VOUT
5V WR
10 0%
0
x - 3
0 DATA
1V 5V 1S
0
TIME - 1s/DIV
-4 -5 0 100 200 300 400 500 BURN-IN TIME @ 150C - HOURS
Figure 19. DAC Output Slew Rate Negative Transition
Figure 16. DAC Full-Scale Out Change vs Time Accelerated by Burn-In
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AD8401
10.0
500mV
9.5
100
VIN = +2.4V
VOUT - 0.5V /DIV
90
CL = 1000pF
SUPPLY CURRENT - mA
V DD = +5V TA = +25C
9.0 8.5 8.0 7.5 7.0 V DD = +4.75V 6.5 6.0 -50 V DD = +5.25V
10 0%
20S
TIME - 20s /DIV
Figure 20. DAC Output Swing with Capacitive Load
-25
0
25
50
75
100
TEMPERATURE - C
Figure 21. Supply Current vs. Temperature
POWER SUPPLY REJECTION - dB
60
TA = +25C OUTPUT = FULL SCALE VDD = 5V 200mV
40
20
0 1k 10k 100k 1M FREQUENCY - Hz
Figure 22. Power Supply Rejection Ratio vs. Frequency
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AD8401
APPLICATIONS INFORMATION
The software programming needs to format data as defined by the transfer equations and Code Tables that follow.
DAC Transfer Equation
The nominal output voltages listed in the Code Table are subject to the static performance specifications. The INL, ZeroScale and Full-Scale errors describe the total specified variation that will be encountered from part to part. One LSB of error for the 2.5 V FS range is 9.766 millivolts (= 2.50/256). Although separate AGNDs exist for both the DAC and ADC to minimize crosstalk, writing data to the DAC while the ADC is performing a conversion may result in an incorrect conversion from the ADC due to signal interaction between the DAC and ADC. Therefore, to ensure correct operation of the ADC, the DAC register should not be updated while the ADC is converting. The AD8401 is configured for an input range of +3.0 volts Full Scale. The nominal transfer characteristic for this range is plotted in Figure 23. The output coding is natural binary with one LSB equal to 11.72 millivolts. Note that the first code transition between 0 LSB and 1 LSB occurs at 5.8 mV, one half of the 11.72 mV LSB step size. The last code transition occurs at Full Scale minus 1.5 LSBs, which is a 2.982 V input. The AD8401 is easily interfaced to most microprocessors by using either address bits or address decode to select the appropriate multiplexer channel. Figure 24 shows how easily the AD8401 interfaces to the AD899. No additional hardware is required.
OUTPUT CODE FULL SCALE TRANSITION
V OUT = 2.500 x
D 255 = 2.500 x for a 2.50 V full scale 256 256
where D is the decimal value 0 through 255 of the 8-bit data word.
Table III. DAC Unipolar Code
Nominal Analog DAC Register Contents Decimal 255 129 128 127 1 0 Binary 1111 1111 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 General Transfer Equation
255 2.500 x 256 2.500 x 2.500 x 2.500 x 129 256 128 256 127 256
Output VOUT 2.490 V 1.260 V 1.250 V 1.240 V 0.010 V 0.000 V
11111111 11111110 11111101
1 2.500 x 256 2.500 x 0 256
1LSB = FS 256 00000011 00000010 FS - 1LSB 00000001 00000000 1 2 3 VIN INPUT VOLTAGE - LSBs FS
Figure 23. ADC 0 V to +3 V Input Transfer Characteristic
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AD8401
ADDRESS BUS
A0 A1 A0 A B C D VIN A VIN B VIN C VIN D
A1
VDD (+5.0V)
AD8401
T/H 8-BIT ADC
1.25V REF
8-BIT DAC
VOUT
AD899
RESET INT BUSY CONTROL LOGIC DAC REG ADC REG
ST
CLOCK
CS
DGND
WR
RD
DATA I/O (8 BITS)
AG DAC
AG ADC
Figure 24. AD8401 Interface to the AD899 Read-Channel Hard Disk Drive Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide-Body SO (SOL-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
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REV. 0
PRINTED IN U.S.A.
C1857-18-10/93

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